Estimation of Clock Skew Using VHDL
نویسنده
چکیده
The clock signal has always been a matter of concern for most of the high–speed functions of the synchronous integrated circuits as it decides the speed regularities. To reduce the irregularities of this signal, the clock skew is one of the major constraints to be taken care of. In this paper, an efficient technique for the estimation of this clock skew has been introduced and VHDL has been used to verify its functionality. The clock skew estimation has been used to pave a way for reducing the speed irregularities of the integrated circuit due to clock skew.
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تاریخ انتشار 2012